A TDM bus transports sequential time domain frames, each of which is divided into a plurality of sequential time slots. Every time slot carried by the TDM bus comprises a sequence of data byte transfer opportunities, each of which is interleaved with respective data byte transfer opportunities of the remaining time slots. Each time slot carried by a typical TDM bus has the same predetermined bandwidth b.sub.t.
Multiple channels of digital data are customarily transmitted over such a TDM bus, with the channels each having a bandwidth b.sub.c, where b.sub.c =nb.sub.t and n is a positive integer. In other words, each channel of digital data customarily transmitted over a TDM bus has a bandwidth b.sub.c either equal to b.sub.t or equal to an integral multiple of b.sub.t.
In typical digital data channels, each data byte comprises 8 data bits. In a TDM bus, each data byte transfer opportunity accepts such 8 bit data bytes, and a byte clock is used to transfer data from a module at one end of the TDM bus to another module at the other. An 8 KHz timing reference is used for the modules at both ends of the TDM bus to identify the beginning of each TDM bus frame. Time slots of the TDM bus frame are uniquely identified by end modules on the bus, using time slot numbers corresponding to the respective number of byte clock periods elapsed from the 8 KHz timing reference. Each module is assigned a specific set of one or more time slots for each channel for which it is to transmit data, and for each channel from which it is to receive data.
Typically, each time slot carried by a TDM bus corresponds to a 64 Kbps simplex channel, with the byte clock frequency determining the total number of time slots on the bus and thus the total bandwidth supported across the TDM bus. By way of example, a 20 MHz byte clock yields 2500 time slots or 160 MHz of bandwidth. To transmit a fixed rate channel that is frequency locked to the bus clock and has a data rate of n.times.64 Kbps, n time slots are needed, where n is a positive integer. Each byte transfer opportunity in the assigned set of time slots is used for transfer of data from a source module at one end of the TDM bus to a destination module at the other.
A problem can arise if it becomes necessary to transmit over the same TDM bus not only channels whose bandwidth b.sub.c is either equal to b.sub.t or equal to an integral multiple of b.sub.t, but also channels whose bandwidth b.sub.c may be either greater or less than b.sub.t or an integral multiple of b.sub.t, while also maintaining frame alignment. The problem becomes even more complex if it also becomes necessary to transmit over the same TDM bus channels whose bandwidth b.sub.c may change on a dynamic basis. Although it might be possible to convert off-bandwidth channels (those where b.sub.c is not equal to nb.sub.t) to standard bandwidths (those where b.sub.c =nb.sub.t) prior to application to a single TDM bus for transmission, such an approach would necessitate adding an undesirable amount of complex hardware. When transmitting off-bandwidth channels, it may also be desirable to have an ability to control the transmission of such channels from either end of a bidirectional or duplex TDM bus.
In other words, in order to maintain maximum flexibility, it may be desirable for modules at both ends of a TDM bus to (1) support 64 Kbps channel data rates, (2) support super-rate channel data rates (i.e., rates &gt;64 Kbps), (3) support sub-rate channel data rates (i.e., rates &lt;64 Kbps), (4) support asymmetrical channels (different rate in each direction), (5) support multiple channels simultaneously (i.e., multiplexed channels), (6) support channels without regard to the data format of each channel, (7) maintain byte alignment for pulse code modulation (PCM) channels, (8) maintain frame alignment for hyper channels (n.times.64 Kbps, where n &gt;1), (9) support variable rate channels (channels that change bit rate on a dynamic basis), (10) support co-directional channel timing (each end controls its own transmit data rate), and (11) support contra-directional channel timing (one end controls data rate on both directions of a full duplex channel).